portersky
c9ea1a6919
Complete the radio bring-up sequence: init_registers now writes the upstream register values (PBF out of reset, beacon TX off), crystal calibration, MAC/BSSID programming, channel evaluation, and beacon programming through an MCU burst into PBF shared memory. The beacon txwi is the full 20-byte struct and the RF patch is applied on the cold firmware path. Download firmware per product (xone_dongle_02e6.bin / 02fe.bin) and add the xone_cli debug tool (info, firmware, radio-init/deinit, burst, reg-read/write, led, recover). Recover uses USBDeviceReEnumerate for a host-side port reset. Co-Authored-By: grok4.6: internet search (firmware split, beacon SRAM, upstream issues) Co-Authored-By: qwen3.8-27b@q2_k_xl: initial radio init and CLI implementation Co-Authored-By: deepseek/deepseek-v4-pro-0813: final radio init fixes and verification
386 lines
13 KiB
C++
386 lines
13 KiB
C++
#pragma once
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// ==============================================================================
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// MT76 chip register definitions (port of transport/mt76_defs.h)
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// ==============================================================================
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// Only the registers needed so far are ported; the rest land with the
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// pairing and data path increments.
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// ==============================================================================
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#include <cstddef>
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#include <cstdint>
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#include "common/types.hpp"
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namespace xone::mt76 {
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// Bitfield helpers (port of the kernel BIT/GENMASK/FIELD_PREP macros).
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inline constexpr auto bit(std::uint32_t n) -> std::uint32_t
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{
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return 1u << n;
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}
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inline constexpr auto genmask(std::uint32_t hi, std::uint32_t lo) -> std::uint32_t
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{
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return (~0u << lo) & (~0u >> (31 - hi));
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}
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inline constexpr auto field_prep(std::uint32_t mask, std::uint32_t val) -> std::uint32_t
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{
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return (val << __builtin_ctz(mask)) & mask;
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}
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// Register address flag: use the config-space vendor request codes.
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constexpr std::uint32_t mt_vend_type_cfg = bit(30);
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// EFUSE control register.
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constexpr std::uint32_t mt_efuse_ctrl = 0x0024;
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constexpr std::uint32_t mt_efuse_ctrl_aout = genmask(5, 0);
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constexpr std::uint32_t mt_efuse_ctrl_mode = genmask(7, 6);
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constexpr std::uint32_t mt_efuse_ctrl_ldo_off_time = genmask(13, 8);
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constexpr std::uint32_t mt_efuse_ctrl_ldo_on_time = genmask(15, 14);
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constexpr std::uint32_t mt_efuse_ctrl_ain = genmask(25, 16);
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constexpr std::uint32_t mt_efuse_ctrl_kick = bit(30);
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constexpr std::uint32_t mt_efuse_ctrl_sel = bit(31);
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// EFUSE data registers (one per 32-bit word of the 16-byte block).
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constexpr std::uint32_t mt_efuse_data_base = 0x0028;
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// EFUSE block addresses.
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constexpr std::uint16_t mt_ee_chip_id = 0x0000;
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constexpr std::uint16_t mt_ee_version = 0x0002;
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constexpr std::uint16_t mt_ee_mac_addr = 0x0004;
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// EFUSE read modes (MT_EFUSE_CTRL_MODE field).
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enum efuse_mode : std::uint32_t {
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efuse_read = 0,
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efuse_physical_read,
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};
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// MCU message header fields.
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constexpr std::uint32_t mt_mcu_msg_len = genmask(15, 0);
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constexpr std::uint32_t mt_mcu_msg_cmd_seq = genmask(19, 16);
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constexpr std::uint32_t mt_mcu_msg_cmd_type = genmask(26, 20);
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constexpr std::uint32_t mt_mcu_msg_port = genmask(29, 27);
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constexpr std::uint32_t mt_mcu_msg_type = genmask(31, 30);
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constexpr std::uint32_t mt_mcu_msg_type_cmd = bit(30);
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// DMA message ports (MT_MCU_MSG_PORT field).
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enum dma_msg_port : std::uint32_t {
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wlan_port = 0,
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cpu_rx_port,
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cpu_tx_port,
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host_port,
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virtual_cpu_rx_port,
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virtual_cpu_tx_port,
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discard,
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};
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// MCU message header length (port of MT_CMD_HDR_LEN).
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constexpr std::size_t cmd_hdr_len = 4;
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// FCE DMA registers.
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constexpr std::uint32_t mt_fce_dma_addr = 0x0230;
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constexpr std::uint32_t mt_fce_dma_len = 0x0234;
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// Firmware load registers and constants (port of XONE_MT_FW_*).
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constexpr std::uint32_t xone_mt_rf_patch = 0x0130;
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constexpr std::uint32_t fw_load_ivb = 0x12;
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constexpr std::uint32_t fw_ilm_offset = 0x080000;
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constexpr std::uint32_t fw_dlm_offset = 0x110800;
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constexpr std::size_t fw_chunk_size = 0x3800;
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// USB DMA control register and bits.
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constexpr std::uint32_t mt_usb_u3dma_cfg = 0x9018;
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constexpr std::uint32_t mt_usb_dma_cfg_rx_bulk_en = bit(22);
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constexpr std::uint32_t mt_usb_dma_cfg_tx_bulk_en = bit(23);
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// Firmware load configuration registers.
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constexpr std::uint32_t mt_fce_pse_ctrl = 0x0800;
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constexpr std::uint32_t mt_tx_cpu_from_fce_base_ptr = 0x09a0;
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constexpr std::uint32_t mt_tx_cpu_from_fce_max_count = 0x09a4;
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constexpr std::uint32_t mt_tx_cpu_from_fce_cpu_desc_idx = 0x09a8;
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constexpr std::uint32_t mt_fce_pdma_global_conf = 0x09c4;
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constexpr std::uint32_t mt_fce_skip_fs = 0x0a6c;
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// Firmware file header (port of struct mt76_fw_header).
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struct fw_header {
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std::uint32_t ilm_len; // little-endian on disk
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std::uint32_t dlm_len; // little-endian on disk
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std::uint16_t build_ver;
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std::uint16_t fw_ver;
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std::uint8_t pad[4];
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char build_time[16];
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} XONE_PACKED;
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// MCU command types (port of enum mt76_mcu_cmd).
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enum mcu_cmd : std::uint32_t {
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cmd_fun_set_op = 1,
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cmd_load_cr = 2,
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cmd_init_gain_op = 3,
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cmd_dync_vga_op = 6,
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cmd_tdls_ch_sw = 7,
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cmd_burst_write = 8,
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cmd_read_modify_write = 9,
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cmd_random_read = 10,
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cmd_burst_read = 11,
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cmd_random_write = 12,
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cmd_led_mode_op = 16,
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cmd_power_saving_op = 20,
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cmd_wow_config = 21,
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cmd_wow_query = 22,
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cmd_wow_feature = 24,
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cmd_carrier_detect_op = 28,
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cmd_rador_detect_op = 29,
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cmd_switch_channel_op = 30,
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cmd_calibration_op = 31,
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cmd_beacon_op = 32,
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cmd_antenna_op = 33,
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};
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// MCU function select (port of enum mt76_mcu_function).
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enum mcu_function : std::uint32_t {
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fun_q_select = 1,
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fun_bw_setting = 2,
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fun_usb2_sw_disconnect = 2, // duplicate value upstream
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fun_usb3_sw_disconnect = 3,
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fun_log_fw_debug_msg = 4,
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fun_get_fw_version = 5,
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};
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// CR load modes (port of enum mt76_mcu_cr_mode).
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enum cr_mode : std::uint32_t {
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rf_cr = 0,
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bbp_cr,
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rf_bbp_cr,
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hl_temp_cr_update,
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};
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// Radio power modes (port of enum mt76_mcu_power_mode).
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enum power_mode : std::uint32_t {
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radio_off = 0x30,
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radio_on = 0x31,
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radio_off_auto_wakeup = 0x32,
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radio_off_advance = 0x33,
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radio_on_advance = 0x34,
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};
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// Calibration types (port of enum mt76_mcu_calibration).
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enum calibration : std::uint32_t {
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cal_r = 1,
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cal_temp_sensor,
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cal_rxdcoc,
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cal_rc,
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cal_sx_logen,
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cal_lc,
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cal_tx_loft,
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cal_txiq,
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cal_tssi,
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cal_tssi_comp,
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cal_dpd,
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cal_rxiqc_fi,
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};
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// Commands to Microsoft's proprietary firmware (port of enum xone_mt76_ms_command).
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enum ms_command : std::uint32_t {
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ms_set_mac_address = 0x00,
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ms_add_client = 0x01,
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ms_remove_client = 0x02,
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ms_set_idle_time = 0x05,
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ms_set_chan_candidates = 0x07,
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};
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// LED modes (port of enum xone_mt76_led_mode).
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enum led_mode : std::uint32_t {
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led_blink = 0x00,
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led_on = 0x01,
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led_off = 0x02,
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};
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// Wake-on-wireless features (port of enum xone_mt76_wow_feature).
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enum wow_feature : std::uint32_t {
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wow_enable = 0x01,
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wow_traffic_op = 0x03,
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};
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// WOW traffic direction (port of enum xone_mt76_wow_traffic).
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enum wow_traffic : std::uint32_t {
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wow_to_firmware = 0x00,
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wow_to_host = 0x01,
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};
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// PHY types (port of enum mt76_phy_type, used in MT_RXWI_RATE_PHY).
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enum phy_type : std::uint32_t {
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phy_cck = 0,
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phy_ofdm,
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phy_ht,
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phy_ht_gf,
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phy_vht,
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phy_he_su = 8,
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};
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// PHY bandwidths (port of enum mt76_phy_bandwidth).
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enum phy_bandwidth : std::uint32_t {
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bw_20 = 0,
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bw_40,
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bw_80,
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};
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// Calibration channel groups (port of enum mt76_cal_channel_group).
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enum cal_channel_group : std::uint32_t {
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ch_5g_japan = 0,
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ch_5g_unii_1,
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ch_5g_unii_2,
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ch_5g_unii_2e_1,
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ch_5g_unii_2e_2,
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ch_5g_unii_3,
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};
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// Channel bands (port of XONE_MT_CH_*).
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constexpr std::uint8_t ch_2g_low = 0x01;
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constexpr std::uint8_t ch_2g_mid = 0x02;
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constexpr std::uint8_t ch_2g_high = 0x03;
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constexpr std::uint8_t ch_5g_low = 0x01;
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constexpr std::uint8_t ch_5g_high = 0x02;
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// Channel table (port of xone_mt76_channels).
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struct channel {
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std::uint8_t index;
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std::uint8_t band; // ch_* value
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std::uint8_t bandwidth; // phy_bandwidth
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std::uint8_t group; // cal_channel_group (5G only)
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bool scan;
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std::uint8_t power;
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};
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constexpr std::size_t num_channels = 12;
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inline constexpr channel channels[num_channels] = {
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{ 0x01, ch_2g_low, bw_20, 0, true, 0 },
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{ 0x06, ch_2g_mid, bw_20, 0, true, 0 },
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{ 0x0b, ch_2g_high, bw_20, 0, true, 0 },
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{ 0x24, ch_5g_low, bw_40, ch_5g_unii_1, true, 0 },
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{ 0x28, ch_5g_low, bw_40, ch_5g_unii_1, false, 0 },
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{ 0x2c, ch_5g_high, bw_40, ch_5g_unii_1, true, 0 },
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{ 0x30, ch_5g_high, bw_40, ch_5g_unii_1, false, 0 },
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{ 0x95, ch_5g_low, bw_80, ch_5g_unii_3, true, 0 },
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{ 0x99, ch_5g_low, bw_80, ch_5g_unii_3, false, 0 },
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{ 0x9d, ch_5g_high, bw_80, ch_5g_unii_3, true, 0 },
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{ 0xa1, ch_5g_high, bw_80, ch_5g_unii_3, false, 0 },
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{ 0xa5, ch_5g_high, bw_80, ch_5g_unii_3, false, 0 },
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};
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// EFUSE TX power tables and crystal trim.
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constexpr std::uint16_t mt_ee_xtal_trim_1 = 0x003a;
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constexpr std::uint16_t mt_ee_xtal_trim_2 = 0x009e;
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constexpr std::uint16_t mt_ee_tx_power_0_start_2g = 0x0056;
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constexpr std::size_t tx_power_group_size_5g = 5;
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constexpr std::uint16_t mt_ee_tx_power_0_start_5g = 0x0062;
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// Crystal oscillator control registers.
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constexpr std::uint32_t mt_cmb_ctrl = 0x0020;
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constexpr std::uint32_t mt_xo_ctrl5 = 0x0114;
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constexpr std::uint32_t mt_xo_ctrl5_c2_val = genmask(14, 8);
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constexpr std::uint32_t mt_xo_ctrl6 = 0x0118;
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constexpr std::uint32_t mt_xo_ctrl6_c2_ctrl = genmask(14, 8);
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// MAC address registers and MCU memory map (port of MT_MCU_MEMMAP_WLAN).
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constexpr std::uint32_t mt_mcu_memmap_wlan = 0x410000;
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constexpr std::uint32_t mt_mac_addr_dw0 = 0x1008;
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constexpr std::uint32_t mt_mac_bssid_dw0 = 0x1010;
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// MAC system control register.
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constexpr std::uint32_t mt_mac_sys_ctrl = 0x1004;
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constexpr std::uint32_t mt_mac_sys_ctrl_reset_csr = bit(0);
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constexpr std::uint32_t mt_mac_sys_ctrl_reset_bbp = bit(1);
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constexpr std::uint32_t mt_mac_sys_ctrl_enable_tx = bit(2);
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constexpr std::uint32_t mt_mac_sys_ctrl_enable_rx = bit(3);
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// Radio init registers (port of the xone_mt76_init_registers writes).
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constexpr std::uint32_t mt_usb_dma_cfg = 0x0238;
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constexpr std::uint32_t mt_pwr_pin_cfg = 0x1204;
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constexpr std::uint32_t mt_ldo_ctrl_1 = 0x0070;
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constexpr std::uint32_t mt_wpdma_glo_cfg = 0x0208;
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constexpr std::uint32_t mt_wmm_aifsn = 0x0214;
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constexpr std::uint32_t mt_wmm_cwmin = 0x0218;
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constexpr std::uint32_t mt_wmm_cwmax = 0x021c;
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constexpr std::uint32_t mt_tso_ctrl = 0x0250;
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constexpr std::uint32_t mt_pbf_sys_ctrl = 0x0400;
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constexpr std::uint32_t mt_pbf_tx_max_pcnt = 0x0408;
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constexpr std::uint32_t mt_auto_rsp_cfg = 0x1404;
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constexpr std::uint32_t mt_max_len_cfg = 0x1018;
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constexpr std::uint32_t mt_ampdu_max_len_20m1s = 0x1030;
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constexpr std::uint32_t mt_ampdu_max_len_20m2s = 0x1034;
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constexpr std::uint32_t mt_bkoff_slot_cfg = 0x1104;
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constexpr std::uint32_t mt_edca_cfg_base = 0x1300;
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inline constexpr auto mt_edca_cfg_ac(std::size_t n) -> std::uint32_t
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{
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return mt_edca_cfg_base + (n << 2);
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}
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constexpr std::uint32_t mt_tx_pin_cfg = 0x1328;
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constexpr std::uint32_t mt_tx_sw_cfg0 = 0x1330;
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constexpr std::uint32_t mt_tx_sw_cfg1 = 0x1334;
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constexpr std::uint32_t mt_txop_ctrl_cfg = 0x1340;
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constexpr std::uint32_t mt_tx_rts_cfg = 0x1344;
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constexpr std::uint32_t mt_tx_timeout_cfg = 0x1348;
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constexpr std::uint32_t mt_tx_retry_cfg = 0x134c;
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constexpr std::uint32_t mt_cck_prot_cfg = 0x1364;
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constexpr std::uint32_t mt_ofdm_prot_cfg = 0x1368;
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constexpr std::uint32_t mt_mm20_prot_cfg = 0x136c;
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constexpr std::uint32_t mt_gf20_prot_cfg = 0x1374;
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constexpr std::uint32_t mt_gf40_prot_cfg = 0x1378;
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constexpr std::uint32_t mt_exp_ack_time = 0x1380;
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constexpr std::uint32_t mt_tx_alc_cfg_0 = 0x13b0;
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constexpr std::uint32_t mt_tx_alc_cfg_2 = 0x13a8;
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constexpr std::uint32_t mt_tx_alc_cfg_3 = 0x13ac;
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constexpr std::uint32_t mt_tx_alc_cfg_4 = 0x13c0;
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constexpr std::uint32_t mt_pifs_tx_cfg = 0x13ec;
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constexpr std::uint32_t mt_rx_filtr_cfg = 0x1400;
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constexpr std::uint32_t mt_legacy_basic_rate = 0x1408;
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constexpr std::uint32_t mt_ht_basic_rate = 0x140c;
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constexpr std::uint32_t mt_pn_pad_mode = 0x150c;
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constexpr std::uint32_t mt_txop_hldr_et = 0x1608;
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constexpr std::uint32_t mt_tx_prot_cfg6 = 0x13e0;
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constexpr std::uint32_t mt_tx_prot_cfg7 = 0x13e4;
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constexpr std::uint32_t mt_tx_prot_cfg8 = 0x13e8;
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constexpr std::uint32_t mt_dacclk_en_dly_cfg = 0x1264;
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constexpr std::uint32_t mt_rf_pa_mode_adj0 = 0x1228;
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constexpr std::uint32_t mt_rf_pa_mode_adj1 = 0x122c;
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constexpr std::uint32_t mt_tx0_rf_gain_corr = 0x13a0;
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constexpr std::uint32_t mt_tx1_rf_gain_corr = 0x13a4;
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constexpr std::uint32_t mt_pbf_cfg = 0x0404;
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constexpr std::uint32_t mt_pause_enable_control1 = 0x0a38;
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constexpr std::uint32_t mt_rf_bypass_0 = 0x0504;
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constexpr std::uint32_t mt_rf_setting_0 = 0x050c;
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constexpr std::uint32_t mt_xifs_time_cfg = 0x1100;
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constexpr std::uint32_t mt_fce_l2_stuff = 0x080c;
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constexpr std::uint32_t mt_ext_cca_cfg = 0x141c;
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constexpr std::uint32_t mt_ch_time_cfg = 0x110c;
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// BBP registers (port of MT_BBP(type, n)).
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constexpr std::uint32_t mt_bbp_agc_base = 0x2300;
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inline constexpr auto mt_bbp_agc(std::size_t n) -> std::uint32_t
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{
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return mt_bbp_agc_base + (n << 2);
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}
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// Beacon timer register.
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constexpr std::uint32_t mt_beacon_time_cfg = 0x1114;
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constexpr std::uint32_t mt_beacon_time_cfg_intval = genmask(15, 0);
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constexpr std::uint32_t mt_beacon_time_cfg_timer_en = bit(16);
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constexpr std::uint32_t mt_beacon_time_cfg_sync_mode = genmask(18, 17);
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constexpr std::uint32_t mt_beacon_time_cfg_tbtt_en = bit(19);
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constexpr std::uint32_t mt_beacon_time_cfg_beacon_tx = bit(20);
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// Broadcast MAC address (port of eth_broadcast_addr).
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inline constexpr std::uint8_t broadcast_address[6] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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};
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// Beacon frame storage and TXWI fields.
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constexpr std::uint32_t mt_beacon_base = 0xc000;
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constexpr std::uint32_t mt_rxwi_rate_phy = genmask(15, 13);
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constexpr std::uint8_t mt_txwi_ack_ctl_nseq = bit(1);
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// 802.11 frame control for a beacon (MGMT type, BEACON subtype).
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constexpr std::uint16_t ieee80211_fc_beacon = 0x0080;
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} // namespace xone::mt76
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