Files
xone_macos/tests/test_mt76.cpp
T
portersky ccc5bc819d feat: port MT76 register and EFUSE access
Add the mt76::chip class on top of the USB transport: 32-bit register
read/write via vendor requests, register polling, and EFUSE reads with
the kick/control sequence from transport/mt76.c. Expose chip_id() and
mac_address() (with the 62:45:bd fallback).

Verified on hardware: chip ID 0x7612 (MT7612) and MAC address read
from EFUSE.

Co-Authored-By: qwen3.8-27b@q2_k_xl: ported register and EFUSE layer
2026-08-17 16:15:56 +02:00

42 lines
1.6 KiB
C++

#include "unity.h"
#include "mt76/mt76_defs.hpp"
void setUp() {}
void tearDown() {}
// Pin the bitfield helpers to kernel BIT/GENMASK/FIELD_PREP semantics.
void test_bitfield_helpers(void)
{
TEST_ASSERT_EQUAL_UINT32(xone::mt76::bit(0), 0x1u);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::bit(30), 0x40000000u);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::genmask(5, 0), 0x3Fu);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::genmask(7, 6), 0xC0u);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::genmask(25, 16), 0x03FF0000u);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::genmask(31, 0), 0xFFFFFFFFu);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::field_prep(xone::mt76::genmask(7, 6), 1), 0x40u);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::field_prep(xone::mt76::genmask(25, 16), 0x01),
0x00010000u);
}
// Pin the EFUSE register layout to transport/mt76_defs.h values.
void test_efuse_registers(void)
{
TEST_ASSERT_EQUAL_UINT32(xone::mt76::mt_efuse_ctrl, 0x0024);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::mt_efuse_ctrl_kick, 0x40000000u);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::mt_efuse_ctrl_ain, 0x03FF0000u);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::mt_efuse_data_base, 0x0028);
TEST_ASSERT_EQUAL_UINT16(xone::mt76::mt_ee_chip_id, 0x0000);
TEST_ASSERT_EQUAL_UINT16(xone::mt76::mt_ee_version, 0x0002);
TEST_ASSERT_EQUAL_UINT16(xone::mt76::mt_ee_mac_addr, 0x0004);
TEST_ASSERT_EQUAL_UINT32(xone::mt76::mt_vend_type_cfg, 0x40000000u);
}
int main(void)
{
UNITY_BEGIN();
RUN_TEST(test_bitfield_helpers);
RUN_TEST(test_efuse_registers);
return UNITY_END();
}